1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and in particular to an improved method for fabricating a semiconductor device which can optimize an electric property of the high integration device, by preventing a device isolation film from being damaged in a contact plug formation process.
2. Description of the Background Art
Recently, the increasingly high integration of semiconductor devices has been remarkably influenced by the development of techniques for forming fine patterns. Especially, it is essential to be able to miniaturize photoresist film patterns used to mask etching or ion implantation processes during the fabrication of semiconductor devices.
Resolution (R) of the photoresist film pattern is proportional to the light source wavelength (xcex) and a process variable (k) of a micro exposure device, and is inversely proportional to a numerical aperture of the exposure device.
R=kxc3x97xcex/NA
Thus, in order to improve optical resolution of the micro exposure device, the wavelength of the light source may be decreased. For example, resolution of the G-line and I-line micro exposure devices having a wavelength of 436 nm and 365 nm is about 0.7 xcexcm and 0.5 xcexcm, respectively. Accordingly, exposure devices using a deep ultraviolet (DUV) light having a small wavelength, for example a KrF laser at 248 nm or an ArF laser at 193 nm, are used to form fine patterns below 0.5 xcexcm. In addition, in order to improve the resolution, various methods have been suggested including using a phase shift mask as a photo mask; adding a contrast enhancement layer (CEL) for enhancing an image contrast on a wafer; using a tri-layer resist (TLR) for positioning an intermediate layer such as a spin on glass (SOG) film between two photoresist films; and a silylation of the photoresist by selectively implanting silicon into the upper portion of a photoresist film.
According to the degree of integration of the semiconductor device, the size of a contact hole connecting upper and lower conductive interconnections and the space between the contact hole and an adjacent interconnection may be decreased, and the aspect ratio of the contact hole may be increased. A highly integrated semiconductor device having multi-layer conductive interconnection requires precise mask alignment in the fabrication process to form the contact hole, thereby reducing process margin.
In order to maintain a space between the contact holes and surrounding interconnections, masks are formed in consideration of and to allow for misalignment tolerance in the mask alignment, lens distortion in the exposure process, critical dimension variation in the mask formation, and photoetching processes, and mask registration offsets.
In addition, there has been taught a self aligned contact (SAC) method for forming a contact hole according to the self alignment method to overcome a disadvantage of the lithography process.
The SAC method may use a polysilicon layer, a nitride film or an oxynitride film as an etch barrier film depending on the process requirements. In general, the nitride film is most commonly employed as the etch barrier film.
Although not illustrated, a conventional SAC method for fabricating a semiconductor device will now be described.
A substructure, for example a device isolation insulation film, a gate insulation film, and a metal-oxide semiconductor field effect transistor (MOSFET) consisting of a gate electrode overlapped with a mask oxide film pattern and source/drain regions is formed on a semiconductor substrate, and an etch barrier film and an interlayer insulation film consisting of an oxide film are sequentially formed over the resultant structure.
A photoresist film pattern is the transformed to expose the interlayer insulation film in the intended contacts region of a storage electrode or bit line on the semiconductor substrate.
The interlayer insulation film exposed by the photoresist film pattern is dry-etched to expose the etch barrier film. A contact hole is then formed by etching the etch barrier film.
In the conventional SAC method for fabricating the semiconductor device, the bit line contact and the storage electrode contact are formed according to the SAC method using the nitride film or oxynitride film. Here, when a protective film is not provided on the device isolation film during the etching process for the interlayer insulation film, the device isolation film will be etched, and thus produce a gate induced drain leakage current, thereby deteriorating the device properties. Accordingly, an SiN or SiON film is deposited to protect the device isolation film during the process of etching the interlayer insulation film.
However, the stress of the SiN film is relatively high, and thus the surface of the active region may still be damaged. For instance, when the SiN film contacts the silicon substrate in the active region, the contact junction leakage current is typically increased by one to three times due to the stress, thereby deteriorating the contact properties and the device operation properties.
Accordingly, it is an object of the present invention to provide a method for fabricating a semiconductor device which can prevent a gate induced drain leakage current from being generated by damage to the device isolation film during the etching process for forming a contact hole according to a self aligned contact process. This object is achieved by forming a protective film at the upper portion of the device isolation film, thereby improving contact resistance properties and device operation properties, by reducing the contact junction leakage current.
Forming a contact hole using a self aligned contact process according to the present invention for fabricating a semiconductor device includes the steps of: forming an insulation film pattern exposing a device isolation region on a semiconductor substrate; forming a trench, by etching the semiconductor substrate using the insulation film pattern as an etching mask; forming an insulation film over the resultant structure; removing the insulation film according to a chemical mechanical polishing process for planarization, by employing the insulation film pattern as an etch barrier or end point; forming a device isolation film, by wet-etching the insulation film using an etching process having an etching selection ratio difference from the insulation film pattern, the device isolation film being formed lower than the semiconductor substrate; forming a protective film over the resultant structure, using a thin film that has an etching selection ratio difference from the device isolation film; removing the protective film on the insulation film pattern using a chemical mechanical polishing process; forming a protective film pattern on the surface of the device isolation film by removing the insulation film pattern; forming a stacked structure of a gate insulation film, a gate electrode and a mask insulation film pattern, and a word line having an insulation film spacer at its sidewalls in the active region of the semiconductor substrate; forming a planarization film over the resultant structure; forming a contact hole by etching the planarization film using a contact mask as an etching mask to expose the intended region for bit line contacts and storage electrode contacts on the active region of the semiconductor substrate; and forming a bit line contact plug and a storage electrode contact plug in the contact holes.